CM0RSTEN=DISABLED, CM4CLKEN=DISABLED, MASTERCPU=M0P, CM4RSTEN=DISABLED, POWERCPU=M0P, CM0CLKEN=DISABLED
CPU Control for multiple processors
| MASTERCPU | Determines which CPU is considered the master. The master CPU cannot have its clock turned off via the related CMnCLKEN bit or be reset via the related CMxRSTEN in this register. The slave CPU wakes up briefly following device reset, then goes back to sleep until activated by the master CPU. 0 (M0P): M0+. Cortex-M0+ is the master CPU. 1 (M4): M4. Cortex-M4 is the master CPU. |
| RESERVED | Reserved. Read value is undefined, only zero should be written… |
| CM4CLKEN | Cortex-M4 clock enable. 0 (DISABLED): Disabled. The Cortex-M4 clock is not enabled. 1 (ENABLED): Enabled. The Cortex-M4 clock is enabled. |
| CM0CLKEN | Cortex-M0+ clock enable. 0 (DISABLED): Disabled. The Cortex-M0+ clock is not enabled. 1 (ENABLED): Enabled. The Cortex-M0+ clock is enabled. |
| CM4RSTEN | Cortex-M4 reset. 0 (DISABLED): Disabled. The Cortex-M4 is not being reset. 1 (ENABLED): Enabled. The Cortex-M4 is being reset. |
| CM0RSTEN | Cortex-M0+ reset. 0 (DISABLED): Disabled. The Cortex-M0+ is not being reset. 1 (ENABLED): Enabled. The Cortex-M0+ is being reset. |
| POWERCPU | Identifies the owner of reduced power mode control: which CPU can cause the device to enter Sleep, Deep Sleep, Power-down, and Deep Power-down modes. 0 (M0P): M0+. Cortex-M0+ is the owner of reduced power mode control. 1 (M4): M4. Cortex-M4 is the owner of reduced power mode control. |
| RESERVED | Reserved. Read value is undefined, only zero should be written… |